The present invention relates to a digital time interval measuring apparatus which is suitable in a digital servo circuit and the like of a video tape recorder.
Units for digitally measuring the time intervals between any two of a plurality of pulses in a parallel manner are typically represented by a digital servo unit of a video tape recorder (VTR). FIG. 1 is a schematic block diagram of a VTR servo unit. In the VTR servo system, two motors, i.e., drum motor 11 for video heads and capstan motor 21 are controlled. Frequency generators 12 and 22 are mounted on the motor spindles of motors 11 and 21, respectively. The outputs from generators 12 and 22 are supplied to wave shapers 13 and 23, respectively. Outputs HFD from wave shapers 13 and 23 are supplied to AFC detectors 14 and 24. The output of detector 14 is fed back to adder 15, and the output of adder 15 is supplied, as a drive signal, to motor 11, via amplifier 16. The output of detector 24 is fed back to adder 25, and the output of adder 25 is supplied, as a drive signal, to motor 21, via amplifier 26. These two feedback loops constitute rotational frequency control systems of motors 11 and 21, respectively, so as to keep the rotational frequency or rotational speed of motors 11 and 21 constant.
The rotational phase control systems of motors 11 and 21 are arranged in the following manner.
On motor 11 side, a signal, representing the rotational phase of a video head, is detected by drum phase detector 17, and the detection signal is wave-shaped by shaper 18. Output HPD from shaper 18 is phase-compared with head reference signal HREF in APC detector 19. The phase difference component obtained by this phase-comparison is mixed with the output from detector 14 by adder 15. The mixed signal from adder 15 is supplied, as the drive signal, to motor 11, via amplifier 16. Then, the rotational phase of the video head is locked with signal HREF.
On motor 21 side, the output of generator 22 is wave-shaped by shaper 23. The obtained wave-shaped output (HFD) is frequency-divided by frequency divider 27. The frequency-divided output from divider 27 is fed back to APC detector 29 via contact R of switch 28 in the recording mode, and is phase-compared with capstan reference signal CREF. A phase difference component, obtained by the comparison, is input to adder 25. A sum of the phase difference component and the output of AFC detector 24 is supplied, as the drive signal, to motor 21, via amplifier 26. Then, the rotational phase of motor 21 is locked at signal CREF (corresponding to signal HREF).
When the VTR is in the recording mode, the output of generator 22 is utilized to control the rotational phase of motor 21. However, when the VTR is in the playback mode, switch 28 is changed to contact P side, and the output of control head 32, which is wave-shaped by shaper 33, is used for the phase control of the motor 21. Control head 32 reproduces a control pulse from tape 31 which is driven by capstan 30. Therefore, in the VTR playback mode, the tape travel position (the phase with respect to the position of the rotational head on the drum) is phase-locked with capstan reference signal CREF.
Now, a means for generating signals HREF and CREF will be described. A vertical sync signal, separated from a video signal, is supplied to input terminal 40.
In the VTR recording mode, the vertical sync signal, separated from the recording video signal, is supplied to reference generator 42 via switch 41. Generator 42 generates a signal synchronized with the vertical sync signal. The signal from generator 42 is frequency-divided by 1/2 frequency divider 43. The output from divider 43 is utilized as signals HREF and CREF.
In the VTR playback mode, switch 41 is turned off. Then, generator 42 free-runs to generate an oscillation signal having the same constant frequency as the vertical sync signal, which is independent of the sync signal from terminal 40. This oscillation signal is used as drum reference signal HREF and is supplied to tracking delay circuit 45 for tracking adjustment. The output of delay circuit 45 is obtained, via contact P of switch 44, as signal CREF. Delay circuit 45 is included to perform tracking adjustment when the mechanical, positional relationships among the video head, the capstan, and the control head are different in different VTRs.
As described above, in a VTR servo unit, system control is performed so that, in the recording mode, a recording pattern matching the standard of the video cassette recorder, such as the VHS system, is maintained and, in the playback mode, the recorded pattern is correctly traced by the video heads.
When a digital measurement means is to be adapted in the circuit system described above, digital measurement means must be provided at generator 42, frequency detector 14 and phase detector 19 of the drum side, and provided at frequency detector 24 and phase detector 29 of the capstan side, resulting in an increased circuit scale.
More specifically, since counters are required in the respective measurement means described above, at least 5 separate counters are required. In addition, each of four detectors 14, 19, 24, and 29 requires at least one latch circuit. In this manner, when a plurality of digital measurement units are merely provided to the respective portions of the circuitry, together with its peripheral circuits, the circuit scale is increased. In order to suppress the increase in circuit scale, a digital servo unit, which can decrease the required number of counters, is proposed.
In this digital servo unit, a cyclic counter serves as a timepiece. Therefore, when a latch pulse is supplied to the timepiece to latch the counter content, the count operation of the counter cannot be stopped. Accordingly, the operation speed of this counter must be set to allow latching of the time by the latch pulse, and to synchronize the count operation and the latch operation. This means that the operation speed of the counter has only a limited margin in consideration of the operation margin. In addition, when a sufficient margin is to be obtained, the number of circuit elements constituting the counter must be increased. Even with the above method, the number of latch circuits is large, and the merit (reduction in circuit scale) of mainly using counters is spoiled.